Verification test method for programmable logic devices

ABSTRACT

A method of efficiently designing, implementing, and verifying programmed PLDs that includes translating simulation test vectors that are generated by design automation software into device level test vectors. Each of the device level test vectors is substantially identical to one of the simulation test vectors and is readable by automatic testers. Thus, the operation of programmed PLDs can be thoroughly and efficiently verified at the device level using the same test stimuli as a simulation test model.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the design process forprogrammable logic devices (PLDs) and, more particularly, to a method ofefficiently designing, implementing, and verifying programmed PLDs.

[0002] A programmable logic device (PLD) is a general-purpose integratedcircuit for implementing logic circuitry. One of the many uses for PLDsis in the control systems on an aircraft. A PLD contains numerous logiccircuit elements that can be customized for a particular application. APLD can be thought of as a collection of logic gates and programmableswitches. The programmable switches are selectively “opened” and“closed” to interconnect the various logic gates to implement a desiredlogic circuit.

[0003] Various types of PLDs are commonly known, and the particular PLDtype utilized depends, at least in part, on the size and complexity ofthe logic circuit being implemented. The PLD types most commonly knowninclude programmable logic arrays (PLAs), programmable array logic (PAL)devices, complex programmable logic devices (CPLDs), and fieldprogrammable gate arrays (FPGAs). A typical PLA may include a pluralityof input buffers and inverters, a plurality of logic AND gates, and aplurality of logic OR gates. The PLA may be programmed to selectivelyinterconnect various of the input buffers and inverters and logic ANDgates, and to selectively interconnect various of the AND gates and ORgates. Thus, a programmed PLA outputs a sum-of-products function of thePLA inputs.

[0004] A typical PAL device, similar to a typical PLA, may also includea plurality of input buffers and inverters, a plurality of logic ANDgates, and a plurality of logic OR gates. However, unlike a PLA, with atypical PAL the OR gates may not be selectively interconnected withvarious of the AND gates. Instead, these interconnections, which canreduce device performance if they are programmable, are fixed. Thus, ascompared to a typical PLA, a typical PAL is simpler to manufacture, lessexpensive, and offers better performance.

[0005] The typical PLAs and PALs described above are useful forimplementing relatively small logic circuits. However, if a relativelylarge logic circuit implementation is required, multiple PLAs or PALsmay be used, or the circuit may be implemented using CPLDs or FPGAs. Atypical CPLD includes a plurality of input/output (I/O) circuits, and aplurality of logic circuit blocks that may be selectively interconnectedby a global interconnection matrix. Each of the logic circuit blocks maybe constructed similar to a PLA or PAL. Thus, a typical CPLD can beviewed as having two levels of programmability. That is, each circuitblock is programmable, and the interconnections between the circuitblocks are programmable.

[0006] A typical FPGA includes a plurality of I/O circuits, a pluralityof configurable logic circuit blocks arranged in a two-dimensionalarray, and a plurality of interspersed switches organized as horizontaland vertical routing channels between rows and columns of theconfigurable logic circuit blocks. Similar to a typical CPLD, a typicalFPGA can be viewed as having two levels of programmability. Each logiccircuit block may be individually programmed to perform a particularlogic function, and the switches may be programmed to selectivelyinterconnect the logic blocks.

[0007] Before installing a PLD in a system, its design and operationshould be verified. In the past, this verification process includedtesting a simulated model of the PLD to verify proper PLD design, andthen testing the actual programmed PLD after it is installed in thesystem to verify its operation. The simulated model testing usesnumerous simulation test vectors (e.g., there is a potential formillions of test vectors) that are generated using design automationsoftware to simulate various input data, and then checks the simulatedmodel output to ensure it functioned properly. For in-system testing,the PLD and various points within the system are instrumented and testsignals are supplied to the PLD inputs. This in-system testing isrelatively labor intensive, time consuming, and costly. In addition,because all of the simulation test vectors may not have been repeated(due to the large number of test vectors), some uncertainty remained inthe operational verification.

[0008] Recently, various certification authorities have published morestringent requirements for verifying proper design and operation ofPLDs. These new requirements include comprehensive PLD operationverification at the device level. Currently, this device level testingis conducted using automated test equipment and a separate set of devicelevel test vectors. These device level test vectors are independentlygenerated using a different set of software tools and are input to theautomated test equipment. Again, due to the large number of simulationtest vectors that are generated by the automated design software, thelikelihood of manually reproducing the simulation test vectors fordevice level testing is quite small. Additionally, the time it takes toindependently generate the device level test vectors is time intensiveand potentially costly.

[0009] Hence, there is a need for a method of verifying proper designand operation of programmed PLDs that is less labor intensive, and/or isless time consuming, and/or provides cost savings over known methods.The present invention addresses one or more of these needs.

SUMMARY OF THE INVENTION

[0010] The present invention provides a method of verifying properdesign and operation of programmed PLDs in which device level testvectors that are substantially identical to simulation test vectors aregenerated during the PLD design process. These device level test vectorsare in a format that is readable by automated test equipment and,therefore, PLD operation can be verified in accordance with morestringent standards with less labor, and/or in less time, and/or withless cost.

[0011] In one embodiment of the present invention, and by way of exampleonly, a method of verifying proper design and operation of a programmedPLD utilizing a PLD test device includes developing, translating, andtesting steps. The developing step includes developing at least onesimulation test vector that is used to test a simulated model of theprogrammed PLD using a design automation software tool. The translatingstep includes translating at least one simulation test vector into atleast one device level test vector that is in a format readable by thePLD test device. The testing step includes testing the programmed PLD inthe PLD test device using each of the device level test vectors toobtain device level test results.

[0012] In another exemplary embodiment of the present invention, amethod of designing, implementing, and verifying proper operation ofprogrammed PLDs includes developing, synthesizing, implementing,translating, and testing steps. One developing step includes developinga software model of the programmed PLD using a design automationsoftware tool. The synthesizing step includes synthesizing the softwaremodel of the programmed PLD using a design synthesis software tool. Theimplementing step includes implementing the programmed PLD based on thesynthesized software model. Another developing step includes developingat least one simulation test vector that is used to test a simulatedmodel of the programmed PLD using the design automation software tool.The translating step includes translating at least one simulation testvector into at least one device level test vector that is in a formatreadable by a PLD test device. The testing step includes testing theprogrammed PLD in the PLD test device using each of the device leveltest vectors to obtain device level test results.

[0013] Other independent features and advantages of the preferred methodwill become apparent from the following detailed description, taken inconjunction with the accompanying drawings which illustrate, by way ofexample, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a flowchart illustrating the overall programmable logicdevice design process according to an embodiment of the presentinvention;

[0015]FIG. 2 is a flowchart depicting various steps of the design phaseof the overall process depicted in FIG. 1;

[0016]FIG. 3 is a flowchart depicting various steps of theimplementation phase of the overall process depicted in FIG. 1;

[0017]FIG. 4 is a flowchart depicting various steps of the verificationphase of the overall process depicted in FIG. 1;

[0018]FIG. 5 illustrates the interrelationships of the various processesdepicted in FIGS. 2, 3, and 4 to make up the overall design processdepicted in FIG. 1; and

[0019]FIG. 6 is a flowchart depicting the operational steps carried outby a simulation test vector software translation tool used in theprocess depicted in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020] Before building a new electrical or electronic system, a set offunctional requirements are developed to describe the desired overallfunction of the system. Based on these functional requirements, systemand circuit designers collaborate and determine how to architect thesystem. In other words, the designers decide which of the systemrequirements will be satisfied with a particular type of hardware.

[0021] In some cases, more particularly those systems that areimplemented using digital technology, the system may include one or moreprogrammable logic devices (PLDs). For example, a PLD may be used tointerface a main processor with other parts of the system, or a PLD maybe used to implement stand-alone functional requirements such as, forexample, an overspeed trip function or watchdog timer. In any event,once it is decided that one or more functions will be implemented usingPLDs, the circuit designers begin working on the design for eachspecific PLD.

[0022] The overall design process for a PLD according to an embodimentof the present invention is depicted in FIG. 1. This overall designprocess 100 includes three major phases, a design phase 200, animplementation phase 300, and a verification phase 400. It is to beappreciated that each of these phases, while depicted in FIG. 1 as beingsequential, include steps that are performed in parallel with steps ofother phases. In any case, in the design phase 200, the source code usedto describe, simulate, and test the overall functionality of the PLD isdeveloped. In the implementation phase 300, the source code issynthesized and is used to program the PLD. In the verification phase400, the synthesized source code is tested and the programmed PLD istested. Each of these different phases will now be discussed in moredetail.

[0023] The first step in the PLD design phase 200 is to develop asoftware model of the programmed PLD logic that describes the overallfunctionality that the PLD will implement 202. This is done using anyone of numerous design automation software tools, such as VHDL andVerilog; preferably, however, VHDL is used. As is generally known, VHDLstands for Very High Speed Integrated Circuit (VHSIC) HardwareDescription Language, and is a programming language that is used todescribe the overall behavior of a digital system or circuit. Similar tohigh-level programming languages, such as Pascal, C, and C++, that allowcomplex design concepts to be expressed as computer programs, VHDL is ageneral-purpose programming language that allows designers to describethe behavior of complex circuits. This software description is in aformat that allows automatic circuit synthesis and circuit simulation,both of which are described more fully below.

[0024] Followed closely after, or in parallel with, the programmed PLDlogic software model development 202, is the development of one or moreso-called “simulation test benches” 204. A simulation test bench is asoftware description of various PLD circuit stimuli and correspondingexpected results files (so-called simulation test vectors) that allowdesigners to test PLD circuit design functionality in a simulated testenvironment. Thus, before a PLD is physically programmed, a simulatedmodel of the programmed PLD can be tested to ensure that it willfunction as it is designed. Preferably, the test benches are writtenusing the same design automation software tool used to develop theprogrammed PLD logic software model (e.g., VHDL). It is noted that whenthe test benches are written, each is preferably written in separatetest sections, which allows each functional section of the PLD to beindividually tested and the test results to be individually tracked.

[0025] Once the programmed PLD logic software model and the simulationtest bench are developed, a simulated model of the programmed PLD istested 206. This is accomplished by translating the developed softwaremodel into the simulated model of the programmed PLD using a simulationsoftware tool and, using this same software tool, subjecting thesimulated model to testing using the test bench simulation test vectors.The results of the simulation test are then checked 208. If the softwaremodel does not meet the design requirements, the PLD logic softwaremodel is revised 210, and the simulation test 206 is repeated until thesoftware model passes. Any one of numerous known software tools may beused to simulate the software model. In a particular preferredembodiment, the simulation software tool is one that is developed byAldec®, Incorporated. Preferably, though certainly not necessarily, thesimulation test vector translation program is run concurrently with thesimulation test bench in this simulation environment.

[0026] Along with the simulation test bench development 204, aspecialized simulation test vector translation program is alsodeveloped. This translation program runs along with the simulation testbench during the simulation testing of the programmed PLD, andtranslates each of the simulation test vectors into device level testvectors that are readable by an automatic test device. The processcarried out by a particular preferred embodiment of a translationprogram is depicted in FIG. 6, and will now be described in detail. Theprogram 600 first initializes the test environment 602. To do this, eachof the simulation test files is placed into a file directory andcompiled into an object code that runs when the simulation is begun.Once the simulation is begun, various variables and signals used tocontrol the sequencing of the simulation are initialized. For each testvector file that is to be created, the program then supplies variousheader information 604 that is needed by the automated test equipment sothat the test equipment can readily discern the meaning of the testvector data with respect to the location on the actual programmed PLD.For example, the pin location of each signal on the device, the type ofsignal (e.g., whether it is an input, an output, or a bi-directionalsignal), and what voltage levels are to be applied and sensed for highand low logic levels, etc. The simulation test vectors are then applied,one at a time, to the simulated model of the programmed PLD 606.

[0027] As each simulation test vector is applied, the simulator awaitsthe response of the simulated model 608, if a delay is programmed intothe simulation test bench. It is noted that a such a delay need not beincluded, but is provided in a preferred embodiment for simulationtesting at the gate level of the programmed PLD model. When the responseis received, it is captured 610 and, along with the input stimulus, isappropriately processed 612. During this processing 612, the captureddata is appropriately categorized as to whether it represents an inputor bi-directional stimulus, or an output or bi-directional response, toensure proper application of the stimulus and monitoring of the responseduring the actual testing of the programmed PLD.

[0028] Thereafter, the processed simulation test vector data istranslated into a device level test vector that is in a format readableby the automated test equipment that will be used to test the actualprogrammed PLD 614. Each of the device level test vectors issubstantially an exact representation of each of the simulation testvectors that is used to test the simulated model of the programmed PLD.These device level test vectors are output, as appropriate, into one ormore vector files, depending on the specific automated test equipmentbeing used 616. In a particular preferred embodiment, there are fourdifferent files, a pull-up vector file, a pull-down vector file, a burstfault vector file, and a pin fault vector file. As is known, the pull-upand pull-down vector files allow tri-state signal testing. Specifically,during a pull-up test, the automated test equipment applies a pull-up toall pins, and during a pull-down test, the test equipment applies apull-down to all pins. A burst fault vector file (which duplicatesexactly the pull-up vector file, except that incorrect response data isperiodically inserted in the test vector data) is used to ensure thatthe test system is operating properly and can detect and report failuresaccurately. A pin fault vector file includes at least one test vectorwith incorrect response data for each pin on the programmed PLD, and isused to ensure that the test system can detect faults that occur on anypin of the PLD, as a result of either an incorrect application of thestimulus or an incorrect response of the PLD.

[0029] During the simulation, the program 600 also monitors the highestedge rate signal in the test, which is typically the high-speed clockdriving the PLD 618. This is done to verify that, during the test,actual testing is being accomplished. If the rising edge does occur,then a counter is incremented 620. This count keeps track of the numberof clock cycles associated with each test vector file. The cycle is thenrepeated until it is determined that all of the simulation test vectorshave been used, meaning the test is complete 622. Once the test iscomplete, the edge count is output to a separate count file, and thepull-up, pull-down, burst fault, and pin fault vector files are closed624. Depending upon the size and number of device level test vectors,the files containing these device level test vectors may be compressedusing any one of numerous known compression software tools 626.

[0030] After the design phase 200 is complete, or in parallel with atleast portions of the design phase 200, the implementation phase 300 isbegun. In the implementation phase 300, the programmed PLD logicsoftware model is synthesized using a design synthesis software tool302. The design synthesis software tool may be any one of numeroussynthesis software tools known in the art. In a preferred embodiment,this tool is one that is developed and marketed by Xilinx®,Incorporated. As is generally known, the synthesis software tooltransforms the text-based format of the programmed PLD logic softwaremodel into a logic-based equivalent PLD program file 304. The PLDprogram file includes a netlist, which is a description of the variouslogic gates and interconnections that are used to implement the logicdesign. The PLD program file may then be downloaded into the physicalPLD to implement the programmed PLD logic 306.

[0031] At this point, or in parallel with portions of the previousphases, the verification phase 400 is begun. During this phase, thedesign is tested to verify that it meets the specified functionalrequirements. This verification testing may include both simulationtesting and actual physical testing of the programmed PLD design.Though, at a minimum actual physical testing of the programmed PLD istested. If the verification phase 400 includes simulation testing, thissimulation testing is conducted on a post-synthesis simulated model ofthe programmed PLD 402. This post-synthesis model, referred to as a“post-route” model, is a gate level model of the programmed PLD logic,and is generated by the synthesis software tool. A simulation softwaretool, which may be the same tool that is used to test the programmed PLDlogic software model during the design phase 200, uses the samesimulation test vectors developed as part of the test bench as stimulifor this simulation testing. These post-synthesis simulation testresults are checked to determine whether or not the PLD program filegenerated by the synthesis software tool functions the same as theprogrammed PLD logic software model. If this simulation test fails, thenthe PLD logic software model may need to be revised, and variousportions of the design 200, implementation 300, and verification 400phases repeated.

[0032] To test the actual programmed PLD, it is mounted on a customcircuit board and is installed into an automatic tester 406. If the PLDis reprogrammable, it may be hard-mounted to this circuit board andprogrammed while installed on the circuit board, or, if it isone-time-programmable (OTP), a socket may be utilized for ease ofreplacement. The automatic tester may be any one of numerous known testdevices known in the art for testing PLDs. For example, in a preferredbut non-limiting embodiment, the automated tester is a devicemanufactured by GenRad®, Incorporated. Once the PLD is installed in theautomatic tester, it is then tested using the device level test vectors410. As was noted above, the files containing these device level testvectors may be compressed and, if so, are first decompressed 408 andthen input to the automatic tester to apply the device level testvectors to the programmed PLD. The results of the test stimuli are thenautomatically compared to the results from the simulation test and, ifthey are equivalent, the programmed PLD is verified at the device level.

[0033] Although the design 200, implementation 300, and verification 400phases have been somewhat described as individual phases, it will beappreciated that this was done only for the sake of convenience. Inreality, each of these phases includes steps that overlap with oneanother. This can be seen more clearly with reference to FIG. 5, whichdepicts the interrelationships of the various phases of the overalldesign process, showing the overlap among the design 200, implementation300, and verification 400 phases.

[0034] With the present embodiment, the simulation test vectors used totest a simulated model of the programmed PLD are translated into devicelevel test vectors that are substantially exact representations of thesimulation test vectors. These device level test vectors in turn areused to test an actual programmed PLD. The simulation test vectors arenumerous, in certain cases running upwards of tens of millions of testvectors. Since the device level test vectors are translated from thesimulation test vectors in a format readable by an automatic tester, theprogrammed PLD's operation can be verified using this same number oftest vectors at the device level in a relatively short period of time.For example, a programmed PLD can be tested with a million or moredevice level test vectors in a matter of minutes.

[0035] While the invention has been described with reference to apreferred embodiment, it will be understood by those skilled in the artthat various changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt to a particularsituation or material to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodiment disclosedas the best mode contemplated for carrying out this invention, but thatthe invention will include all embodiments falling within the scope ofthe appended claims.

We claim:
 1. A method of verifying proper design and operation of aprogrammed programmable logic device (PLD) utilizing a PLD test device,comprising: developing at least one simulation test vector using a PLDdesign automation software tool, each simulation test vector used totest a simulated model of the programmed PLD; translating at least onesimulation test vector into at least one device level test vector thatis in a format readable by the PLD test device; and testing theprogrammed PLD in the PLD test device using each of the device leveltest vectors to obtain device level test results.
 2. The method of claim1, wherein all of the simulated test vectors are translated into acorresponding device level test vector.
 3. The method of claim 1,further comprising: testing the simulated model of the programmed PLDusing each of the simulation test vectors to obtain simulation testresults; and comparing the simulation test results with the device leveltest results.
 4. The method of claim 1, further comprising: developing asoftware model of the programmed PLD using the design automationsoftware tool; and translating the software model of the programmed PLDinto the simulated model of the programmed PLD using a simulationsoftware tool.
 5. The method of claim 4, wherein the simulation softwaretool translates the simulation test vectors into the device level testvectors.
 6. The method of claim 5, wherein each of the device level testvectors include stimulus data and expected results data.
 7. The methodof claim 1, further comprising: generating at least one data file; andstoring each of the device level test vectors in the data files.
 8. Themethod of claim 7, further comprising: compressing the data files;storing the compressed data files on a memory storage device; anddecompressing the compressed data files to recover the device level testvectors.
 9. The method of claim 1, further comprising: developing asoftware model of the programmed PLD using a design automation softwaretool; and synthesizing the software model of the programmed PLD using adesign synthesis software tool.
 10. The method of claim 9, furthercomprising: generating a PLD program file from the synthesized softwaremodel.
 11. The method of claim 10, further comprising: downloading thePLD program file into an integrated PLD circuit to create the programmedPLD.
 12. The method of claim 1, further comprising: developing asoftware model of the programmed PLD using a design automation softwaretool; synthesizing the software model of the programmed PLD using adesign synthesis software tool; translating the synthesized softwaremodel into a post-synthesis simulated model of the programmed PLD usingthe simulation software; and testing the post-synthesis simulated modelof the programmed PLD using each of the simulation test vectors toobtain post-synthesis simulation test results.
 13. A method of verifyingproper design and operation of a programmed programmable logic device(PLD) utilizing a PLD test device, comprising: developing at least onesimulation test vector using PLD a design automation software tool, eachsimulation test vector useful for testing a simulated model of theprogrammed PLD; translating at least one simulation test vector into atleast one device level test vector that is in a format readable by thePLD test device; testing the programmed PLD in the PLD test device usingeach of the device level test vectors to obtain device level testresults; testing the simulated model of the programmed PLD using each ofthe simulation test vectors to obtain simulation test results; andcomparing the simulation test results with the device level testresults.
 14. The method of claim 13, wherein all of the simulated testvectors are translated into a corresponding device level test vector.15. The method of claim 13, further comprising: developing a softwaremodel of the programmed PLD using the design automation software tool;and translating the software model of the programmed PLD into thesimulated model of the programmed PLD using a simulation software tool.16. The method of claim 15, wherein the simulation software tooltranslates the simulation test vectors into the device level testvectors.
 17. The method of claim 16, wherein each of the device leveltest vectors include stimulus data and expected results data.
 18. Themethod of claim 13, further comprising: generating at least one datafile; and storing each of the device level test vectors in the datafiles.
 19. The method of claim 18, further comprising: compressing thedata files; storing the compressed data files on a memory storagedevice; and decompressing the compressed data files to recover thedevice level test vectors.
 20. The method of claim 13, furthercomprising: developing a software model of the programmed PLD using adesign automation software tool; and synthesizing the software model ofthe programmed PLD using a design synthesis software tool.
 21. Themethod of claim 20, further comprising: generating a PLD program filefrom the synthesized software model.
 22. The method of claim 21, furthercomprising: downloading the PLD program file into an integrated PLDcircuit to create the programmed PLD.
 23. The method of claim 13,further comprising: developing a software model of the programmed PLDusing a design automation software tool; synthesizing the software modelof the programmed PLD using a design synthesis software tool;translating the synthesized software model into a post-synthesissimulated model of the programmed PLD using the simulation software; andtesting the post-synthesis simulated model of the programmed PLD usingeach of the simulation test vectors to obtain post-synthesis simulationtest results.
 24. A method of verifying proper design and operation of aprogrammed programmable logic device (PLD) utilizing a PLD test device,comprising: developing a software model of the programmed PLD using adesign automation software tool; translating the software model of theprogrammed PLD into a simulated model of the programmed PLD using asimulation software tool; developing at least one simulation test vectorusing PLD the design automation software tool, each simulation testvector used to testing the simulated model of the programmed PLD;translating at least one simulation test vector into at least one devicelevel test vector that is in a format readable by a PLD test device;testing the programmed PLD in the PLD test device using each of thedevice level test vectors to obtain device level test results; testingthe simulated model of the programmed PLD using each of the simulationtest vectors to obtain simulation test results; and comparing thesimulation test results with the device level test results.
 25. A methodof designing, implementing, and verifying proper operation of programmedprogrammable logic devices (PLDs), comprising: developing a softwaremodel of the programmed PLD using a design automation software tool;synthesizing the software model of the programmed PLD using a designsynthesis software tool; implementing the programmed PLD based on thesynthesized software model; developing at least one simulation testvector using the design automation software tool, each simulation testvector useful for testing a simulated model of the programmed PLD;translating each simulation test vector into at least one device leveltest vector that is in a format readable by a PLD test device; andtesting the programmed PLD in the PLD test device using each of thedevice level test vectors to obtain device level test results.
 26. Themethod of claim 25, wherein all of the simulated test vectors aretranslated into a corresponding device level test vector.
 27. The methodof claim 25, further comprising: testing the simulated model of theprogrammed PLD using each of the simulation test vectors to obtainsimulation test results; and comparing the simulation test results withthe device level test results.
 28. The method of claim 25, furthercomprising: translating the software model of the programmed PLD intothe simulated model of the programmed PLD using a simulation softwaretool.
 29. The method of claim 28, wherein the simulation software tooltranslates the simulation test vectors into the device level testvectors.
 30. The method of claim 25, wherein each of the device leveltest vectors includes stimulus data and expected results data.
 31. Themethod of claim 25, further comprising: generating at least one datafile; and storing each of the device level test vectors in the datafiles.
 32. The method of claim 31, further comprising: compressing thedata files; storing the compressed data files on a memory storagedevice; and decompressing the compressed data files to recover thedevice level test vectors.
 33. The method of claim 25, wherein the stepof implementing the programmed PLD comprises: generating a PLD programfile from the synthesized software model; and downloading the PLDprogram file into an integrated PLD circuit to create the programmedPLD.
 34. The method of claim 25, further comprising: translating thesynthesized software model into a post-synthesis simulated model of theprogrammed PLD using the simulation software; and testing thepost-synthesis simulated model of the programmed PLD using each of thesimulation test vectors to obtain post-synthesis simulation testresults.
 35. A method of designing, implementing, and verifying properoperation of programmed programmable logic devices (PLDs), comprising:developing a software model of the programmed PLD using a designautomation software tool; synthesizing the software model of theprogrammed PLD using a design synthesis software tool; implementing theprogrammed PLD based on the synthesized software model; developing atleast one simulation test vector using the design automation softwaretool, each simulation test vector useful for testing a simulated modelof the programmed PLD; translating at least one simulation test vectorinto at least one device level test vector that is in a format readableby a PLD test device; testing the simulated model of the programmed PLDusing each of the simulation test vectors to obtain simulation testresults; testing the programmed PLD in the PLD test device using each ofthe device level test vectors to obtain device level test results; andcomparing the simulation test results with the device level testresults.
 36. A method of translating simulation test vectors used totest a simulated model of a programmed programmable logic device (PLD)into device level test vectors used to test the programmed PLD, themethod comprising: applying at least one simulation test vector to asimulated model of the programmed PLD; capturing a response of thesimulated model to the applied simulation test vector; and convertingthe simulation test vector and captured response into a format readableby a PLD test device.
 37. The method of claim 36, further comprising:categorizing the simulation test vector as one of an input stimulus anda bi-directional stimulus; and categorizing the captured response as oneof an output response and a bi-directional response.
 38. The method ofclaim 36, further comprising: outputting the simulation test vector to apredetermined file.
 39. The method of claim 38, wherein thepredetermined file is one of a pull-up file, a pull-down file, a burstfault file, and a pin fault file.
 40. The method of claim 36, furthercomprising: monitoring an occurrence of a rising edge of a predeterminedsignal; and incrementing a counter with each occurrence of the risingedge to obtain a total count.
 41. The method of claim 40, furthercomprising: outputting the total count to a count file.
 42. A computerimplemented system for translating simulation test vectors used to testa simulated model of a programmed programmable logic device (PLD) intodevice level test vectors used to test the programmed PLD, the systemcomprising: means for applying at least one simulation test vector to asimulated model of the programmed PLD; means for capturing a response ofthe simulated model to the applied simulation test vector; and means forconverting the simulation test vector and captured response into aformat readable by a PLD test device.
 43. The system of claim 42,further comprising: means for categorizing the simulation test vector asone of an input stimulus and a bi-directional stimulus; and categorizingthe captured response as one of an output response and a bi-directionalresponse.
 44. The system of claim 42, further comprising: means foroutputting the simulation test vector to a predetermined file.
 45. Thesystem of claim 44, wherein the predetermined file is one of a pull-upfile, a pull-down file, a burst fault file, and a pin fault file. 46.The system of claim 42, further comprising: means for monitoring anoccurrence of a rising edge of a predetermined signal; and means forincrementing a counter with each occurrence of the rising edge to obtaina total count.
 47. The system of claim 46, further comprising:outputting the total count to a count file.
 48. A computer-readablestorage medium containing computer executable code for instructing acomputer to perform steps that translate simulation test vectors used totest a simulated model of a programmed programmable logic device (PLD)into device level test vectors used to test the programmed PLD, thesteps comprising: applying at least one simulation test vector to asimulated model of the programmed PLD; capturing a response of thesimulated model to the applied simulation test vector; and convertingthe simulation test vector and captured response into a format readableby a PLD test device.
 49. The storage medium of claim 48, furthercomprising the steps of: categorizing the simulation test vector as oneof an input stimulus and a bi-directional stimulus; and categorizing thecaptured response as one of an output response and a bi-directionalresponse.
 50. The storage medium of claim 48, further comprising thesteps of: outputting the simulation test vector to a predetermined file.51. The storage medium of claim 50, wherein the predetermined file isone of a pull-up file, a pull-down file, a burst fault file, and a pinfault file.
 52. The storage medium of claim 48, further comprising thesteps of: monitoring an occurrence of a rising edge of a predeterminedsignal; and incrementing a counter with each occurrence of the risingedge to obtain a total count.
 53. The storage medium of claim 52,further comprising the steps of: outputting the total count to a countfile.